Along with the increasing demand of more powerful computing capability in devices, such as notebook computers, mobile phones, global positioning systems (GPS), and autonomous vehicle systems and higher resolution of full-spectrum display devices, such as mobile phone displays, TV panels, and computer screens, patterning techniques forming electronic circuits on a substrate wafer pushes the edge-to-edge or end-to-end (in short “EE”) distance or length in a patterned line along a width direction in the patterned line to the lowest possible value. Traditionally, a sub-micron lithography technique and an etching method using a mask are used to form device/circuit patterns on a substrate wafer. The lithographic techniques use electromagnetic waves such as ultra violet (UV) photolithography, deep UV (DUV) photolithography, x-ray lithography, etc. The wavelengths pose a limit for the smallest dimension that can be formed through a gap of a mask. Other methods such as dip-pen lithography and electron beam lithography also pose a limit to the smallest dimension that can be formed. Since synthesized nanostructures (such as nanotube, nanorod, etc.) have a dimension that can be smaller than the smallest dimension of photolithographic methods, a bottom-up method by growing nanostructures on a substrate using a deposition method, such as such as chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), such as pulsed laser deposition (PLD), sputtering, evaporative deposition, etc. can be used to form the nanostructures. However, manipulation of the formed nanostructures into aligned electronic devices on a substrate is very challenging and time consuming, and is thus usually carried out only in laboratory scale but not in industry scale. Therefore, there is a demand for a method that can be used to form fine line patterned with EE pushed to a new low level in industry scale.